1. Field of the Invention
The present invention relates to an apparatus and method for testing a semiconductor integrated circuit, and more particularly to an apparatus for testing a semiconductor integrated circuit including an A/D (analog-to-digital) converter circuit for converting an analog signal into a digital signal and a D/A (digital-to-analog) converter circuit for converting a digital signal into an analog signal.
2. Background Art
Recently, in relation to a system LSI embodied in a one-chip semiconductor integrated circuit (a one-chip LSI) consisting of a plurality of functionally-systematized circuit modules or embodied in a hybrid integrated circuit (a chip set LSI), combination of high performance and precision digital and analog circuits (i.e., a system LSI handling a mixed signal) has been rapidly pursued. Even in relation to a test apparatus for use with a semiconductor integrated circuit, development of a test apparatus capable of handling a mixed signal is also pursued. Tester manufacturers have provided testers coping with a semiconductor integrated circuit using a mixed signal.
A tester compatible with a semiconductor integrated circuit using a mixed signal has a tendency to become expensive in order to comply with high performance specifications. For this reason, moves are afoot to recycle an existing low-speed, low-precision tester which has been used for, e.g., a logic LSI, to thereby avoid a hike in the price of a tester.
A big problem with such a test apparatus lies in a characteristic test for a D/A converter circuit for converting a digital signal into an analog signal (digital-to-analog converter, hereinafter called a xe2x80x9cDACxe2x80x9d) as well as in a characteristic test for an A/D converter circuit for converting an analog signal into a digital signal (hereinafter called an xe2x80x9cADCxe2x80x9d). In association with an increase in the precision of the characteristic test, embodiment of a low-cost test apparatus compatible with a semiconductor integrated circuit including the DAC and ADC has posed a challenge.
In a testing environment of a general tester, a plurality of DUT (device under test) circuit boards (simply called xe2x80x9cDUT boardsxe2x80x9d) and connection jigs for connecting a tester with a DUT, such as cables, are provided at arbitrary points along a measurement path extending from measurement equipment provided in the tester to a semiconductor integrated circuit under test (hereinafter called a xe2x80x9cDUTxe2x80x9d). Further, the measurement path is long and accounts for occurrence of noise and a drop in measurement accuracy. Further, simultaneous testing of a plurality of DUTs is also impossible. A limitation is imposed on the speed of a low-speed tester, and hence the low-speed tester cannot conduct a test at a real operating speed, thereby posing a fear of an increase in a time required for conducting mass-production testing of a system LSI.
Japanese Patent Application Laid-Open No. 316024/1989 describes a tester. The tester is equipped with a memory device for storing conversion data at an address designated by input data which have been entered into a DAC of a test circuit. An analog signal which has been subjected to digital-to-analog conversion is input to an ADC, and an output from the ADC is sequentially stored in the memory device. After conversion of all the input data sets has been completed, the conversion data stored in the memory device are sequentially delivered to a tester. The tester sequentially compares the input data with the conversion data, thus producing a test conclusion.
However, the tester must supply data to be input to the DAC, an address to be used for storing conversion data into a memory device, and a control signal. Moreover, data stored in the memory device must be supplied to the tester. Further, there is the probability that noise arising in a long measurement path extending from the tester to a DUT may deteriorate precision of measurement. Further, the majority of pin electronics provided on the tester are occupied for testing a single DUT, thereby posing a difficulty in simultaneous measurement of a plurality of DUTs.
Further, communication for transmitting conversion data to the tester is time consuming, and test conclusions are produced after completion of all tests. Hence, shortening of a test time is also difficult.
The present invention has been conceived to solve such a problem and is aimed at providing an apparatus and method of testing a semiconductor integrated circuit, which apparatus and method enable testing of various semiconductor integrated circuits having different characteristics, fulfillment of the function of generating DAC data, and adaptation of various analog characteristic tests.
According to one aspect of the present invention, an apparatus for testing a semiconductor integrated circuit comprises a test circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested that comprises an A/D converter circuit to convert analog signals to digital signals and a D/A converter circuit to convert digital signals to analog signals, a test ancillary device which is disposed in the vicinity of the test circuit board and is connected to the test circuit board, and an external controller connected to the test ancillary device. The test ancillary device comprises a data circuit which produces a digital test signal and supplies the digital test signal to the D/A converter circuit of the semiconductor integrated circuit to be tested, a testing D/A converter circuit which converts the digital test signal from the data circuit into an analog test signal and supplies the analog test signal to the A/D converter circuit of the semiconductor integrated circuit to be tested, a register circuit which is provided in the data circuit and is arranged so as to be able to change the number of bits of digital input of the D/A converter circuit of the semiconductor integrated circuit to be tested and the number of bits of digital input of the testing D/A converter circuit matching the measurement resolution of the A/D converter circuit of the semiconductor integrated circuit to be tested, a testing A/D converter circuit which converts an analog test output from the D/A converter circuit of the semiconductor integrated circuit to be tested into a digital test output, measured data memory for storing a digital test output from the A/D converter circuit of the semiconductor integrated circuit to be tested and the digital test output from the testing A/D converter circuit, and an analysis section for analyzing the each digital test outputs stored in the measured data memory, The digital test signal and the analog test signal are imparted to the semiconductor integrated circuit to be tested in accordance with an instruction from the external controller, and a result of analysis of the each digital test outputs stored in the measured data memory, the analysis being performed by the analysis section, is sent to the external controller.
According to another aspect of the present invention, an apparatus for testing a semiconductor integrated circuit comprises a test circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested that comprises an A/D converter circuit to convert analog signals to digital signals and a D/A converter circuit to convert digital signals to analog signals, a test ancillary device which is disposed in the vicinity of the test circuit board and is connected to the test circuit board, and a tester connected to the test ancillary device. The test ancillary device comprises look-up memory which stores required data beforehand, outputs data by sequentially updating an output from a memory address counter for supplying an address of the required data, and supplies the data as a digital test signal to the D/A converter circuit of the semiconductor integrated circuit to be tested, a testing D/A converter circuit which converts the digital test signal output from the look-up memory into an analog test signal and supplies the analog test signal to the A/D converter circuit of the semiconductor integrated circuit to be tested, a testing A/D converter circuit which converts an analog test output from the D/A converter circuit of the semiconductor integrated circuit to be tested into a digital test output, measured data memory for storing a digital test output from the A/D converter circuit of the semiconductor integrated circuit to be tested and the digital test output from the testing A/D converter circuit, and an analysis section for analyzing the each digital test outputs stored in the measured data memory. The digital test signal and the analog test signal are imparted to the semiconductor integrated circuit to be tested in accordance with an instruction from the tester, and a result of analysis of the each digital test outputs stored in the measured data memory, the analysis being performed by the analysis section, is sent to the tester.
According to another aspect of the present invention, an apparatus for testing a semiconductor integrated circuit comprises a test circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested that comprises an A/D converter circuit to convert analog signals to digital signals and a D/A converter circuit to convert digital signals to analog signals, a test ancillary device which is disposed in the vicinity of the test circuit board and is connected to the test circuit board, and a tester connected to the test ancillary device. The test ancillary device comprises an analysis section which produces a digital test signal by an arithmetic function and supplies the digital test signal to the D/A converter circuit of the semiconductor integrated circuit to be tested, a testing D/A converter circuit which converts the digital test signal output from the analysis section into an analog test signal and supplies the analog test signal to the A/D converter circuit of the semiconductor integrated circuit to be tested, a testing A/D converter circuit which converts an analog test output from the D/A converter circuit of the semiconductor integrated circuit to be tested into a digital test output, and measured data memory for storing a digital test output from the A/D converter circuit of the semiconductor integrated circuit to be tested and a digital test output from the testing A/D converter circuit. The analysis section analyzes the each digital test outputs stored in the measured data memory.
According to another aspect of the present invention, there is provided a test method for testing a semiconductor integrated circuit, in which a test is conducted through use of one of the test apparatuses as described above.
A test apparatus and method according to the present invention enables switching of a range in accordance with the level of an output from a DAC for test purpose provided in a BOST device or with the level of an output from the DAC during an analog test. Hence, the test apparatus and method can be applied to measurement of DUTs of different types which have different analog output voltage levels or analog input voltage levels.
According to the test apparatus and method according to the present invention, required data which have been computed beforehand are stored in lookup memory, and a memory address counter which supplies an address of the lookup memory is updated sequentially, so that data are output from the memory address counter. The thus-output data are set as a digital test signal. By means of storing, into memory, a required number of DAC input data sets which take into consideration the number of bits and repetitions required by the DAC, measurement of analog circuits of different types can be effected. Thus, the test apparatus and method can cope with evaluation of design of an analog circuit and adaptation to a variety of analog characteristic tests.
Other and further objects, features and advantages of the invention will appear more fully from the following description.